Welcome to PᴺCEL's website!
Great thanks to Apple for sponsoring the UW ECE chip tape-out courses (Prof. Chris Rudell's analog tape-out series and Ang Li 's digital tape-out series)!
All-Digital Bluetooth Low Energy (BLE) Backscatter ASIC using Standard I/O Pad Drivers in 180 nm CMOS accepted to RFID 2026, congrats to Ryan, Kate, Te Min, Andrew Pan (undergraduate team on Ang Li 's digital VLSI tape-out class, EE 478, Spr 2025) and our collaborators from Prof. Matt Reynolds' research lab!
DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays accepted to ISCA 2026, congrats to Jiayi Wang, Darren Lu, and Zhichen Zeng!
"STEP: Spatially Threaded Execution Pipeline" accepted to the LATTE workshop at ASPLOS 2026, congrats to Darren Lu and Jiayi Wang!
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines accepted as a short paper at FCCM 2026, congrats to Jiayi Wang, Maohua, and Sin-Chen!
Precision-aware Communication in CGRAs accepted as a poster at FCCM 2026. Congrats to Shwet Chitnis, Fergus Xu, Rampranav Navendran, Ayush Kulkarni, and all!
"piPE-SA: Enabling Deeply Pipelined Processing Elements in Systolic Arrays" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jiayi Wang and Chenyi Wang!
"CacheFlex: Explicitly Control What You Need in Your Cache" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jingqun Zhang, Yung-Jen Cheng, Jiayi Wang, Shwet Chitnis, and all!
Tactic: Adaptive Sparse Attention with Clustering and Distribution Fitting for Long-Context LLMs and Local Linear Attention: An Optimal Interpolation of Linear and Softmax Attention For Test-Time Regression accepted to ICLR 2026, congrats to Zhichen Zeng and our collaborators!
Zhichen Zeng is selected for the 2025-2026 Meta AI Mentorship program. Congrats!