Edge, physical, and embodied AI mix AI with ordinary computation, serve one request at a time instead of a full batch, and live inside a fixed power and size budget. The answers that work for cloud serving do not carry over.
Transistor scaling has ended, so efficiency now has to come from moving work up the stack. We make hardware simpler and cheaper, and ask compilers, runtimes, and programmers to carry what they are already better at.
We tape out chips and release open-source infrastructure, because a claim about efficiency is only as good as the silicon behind it.
Ang gave an invited talk titled Advancing Efficiency with (Re-)Configurable Hardware at Boeing.
Welcome Yongsheng, our new PhD!
UW ECE's Training the next generation of microchip designers features our digital VLSI tape-out course, taught by Ang, alongside UW ECE's analog VLSI tape-out course taught by Prof. Chris Rudell.
Ang gave an invited talk titled Modern AI Infrastructure and the Chips Inside to Winbond managers at UW Foster School of Business.
Step-dLLM: Adaptive Step-aware Sparse Attention for Efficient Diffusion LLM Inference accepted to NeurIPS 2026, congrats to Zhichen and our collaborators!
MFSA: A Multi-Format Systolic Array with Native Micro Scaling Support accepted to ICCD 2026, congrats to Jiayi and Kearnan!
Ang gave invited talks titled Advancing Efficiency with (Re-)Configurable Hardware at Nvidia Research, AMD, Apple, Meta, UC Berkeley, and Efficient Computer.
CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support accepted to MICRO 2026, congrats to Jingqun, Maohua, Jiayi, Weihang, Rishi, Shwet!
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