Welcome to PᴺCEL's website!
DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays accepted to ISCA 2026, congrats to Jiayi Wang, Darren Lu, and Zhichen Zeng!
"STEP: Spatially Threaded Execution Pipeline" accepted to the LATTE workshop at ASPLOS 2026, congrats to Darren Lu and Jiayi Wang!
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines accepted as a short paper at FCCM 2026, congrats to Jiayi Wang, Maohua, and Sin-Chen!
Precision-aware Communication in CGRAs accepted as a poster at FCCM 2026. Congrats to Shwet Chitnis, Fergus Xu, Rampranav Navendran, Ayush Kulkarni, and all!
"piPE-SA: Enabling Deeply Pipelined Processing Elements in Systolic Arrays" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jiayi Wang and Chenyi Wang!
"CacheFlex: Explicitly Control What You Need in Your Cache" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jingqun Zhang, Yung-Jen Cheng, Jiayi Wang, Shwet Chitnis, and all!
Two papers accepted to ICLR 2026, congrats to Zhichen Zeng!
Zhichen Zeng is selected for the 2025-2026 Meta AI Mentorship program. Congrats!
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Welcome our first PhD cohort, Jiayi Wang, Jingqun Zhang, Darren Lu, and Zhichen Zeng!