Personal Statement

This person is busy changing the world...

News

Jiayi and Jingqun will join NVIDIA this summer — Computer Performance Intern and GPU Profiling & Tools Intern. Congrats!

All-Digital Bluetooth Low Energy (BLE) Backscatter ASIC using Standard I/O Pad Drivers in 180 nm CMOS accepted to RFID 2026, congrats to Ryan, Kate, Tyoma, Andrew (undergraduate team on Ang 's digital VLSI tape-out class, EE 478, Spr 2025) and our collaborators from Prof. Matt Reynolds' research lab!

"STEP: Spatially Threaded Execution Pipeline" accepted to the LATTE workshop at ASPLOS 2026, congrats to Darren and Jiayi!

"piPE-SA: Enabling Deeply Pipelined Processing Elements in Systolic Arrays" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jiayi and Chenyi!

"CacheFlex: Explicitly Control What You Need in Your Cache" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jingqun, Yung-Jen, Jiayi, Shwet, and all!

Welcome our first PhD cohort, Jiayi, Jingqun, Darren, and Zhichen!

Publications

CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support

Jingqun Zhang, Maohua Nie, Jiayi Wang, Weihang Li, Rishi Sappidi, Shwet Chitnis, Ang Li

59th IEEE/ACM International Symposium on Microarchitecture, Oct 2026

DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays

Jiayi Wang, Darren Lu, Zhichen Zeng, Ang Li

The 53rd IEEE/ACM International Symposium on Computer Architecture, Jun 2026

arXiv
@article{Wang2026DICE,
	author = {Wang, Jiayi and Da Lu, Ang and Zeng, Zhichen and Li, Ang},
	doi = {10.48550/ARXIV.2605.05496},
	year = {2026},
	publisher = {arXiv},
	title = {DICE: Enabling {Efficient} {General}-{Purpose} {SIMT} {Execution} with {Statically} {Scheduled} {Coarse}-{Grained} {Reconfigurable} {Arrays}},
	url = {https://arxiv.org/abs/2605.05496},
}

All-Digital Bluetooth Low Energy (BLE) Backscatter ASIC using Standard I/O Pad Drivers in 180 nm CMOS

Ryan Lee, Kate Tseng, Te Min "Tyoma" Yu, Andrew Pan, Jiayi Wang, James Rosenthal, Kevin J Ho, Ang Li, Matthew Reynolds

2026 IEEE International Conference on RFID, Jun 2026

TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines

Jiayi Wang, Maohua Nie, Sin-Chen Lin, C. -J. Richard Shi, Ang Li

The 34th IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2026

DOIarXiv
@inproceedings{Wang2026TransDot,
	author = {Wang, Jiayi and Nie, Maohua and Lin, Sin-Chen and Shi, C.-J. Richard and Li, Ang},
	booktitle = {2026 {IEEE} 34th {Annual} {International} {Symposium} on {Field}-{Programmable} {Custom} {Computing} {Machines} ({FCCM})},
	doi = {10.1109/fccm68464.2026.00034},
	year = {2026},
	month = {may 13},
	pages = {171--175},
	organization = {IEEE},
	title = {TransDot: An {Area}-efficient {Reconfigurable} {Floating}-{Point} {Unit} for {Trans}-{Precision} {Dot}-{Product} {Accumulation} for {FPGA} {AI} {Engines}},
	url = {http://dx.doi.org/10.1109/FCCM68464.2026.00034},
}

@article{Wang2026TransDot,
	author = {Wang, Jiayi and Nie, Maohua and Lin, Sin-Chen and Shi, C. -J. Richard and Li, Ang},
	doi = {10.48550/ARXIV.2605.07245},
	year = {2026},
	publisher = {arXiv},
	title = {TransDot: An {Area}-efficient {Reconfigurable} {Floating}-{Point} {Unit} for {Trans}-{Precision} {Dot}-{Product} {Accumulation} for {FPGA} {AI} {Engines}},
	url = {https://arxiv.org/abs/2605.07245},
}

Precision-aware Communication in CGRAs

Shwet Chitnis, Fergus Xu, Ayush Kulkarni, Jiayi Wang, Jingqun Zhang, Arjun Raje, Ang Li

The 34th IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2026

DisagMoE: Computation-Communication overlapped MoE Training via Disaggregated AF-Pipe Parallelism

Zhichen Zeng, Chi-Chih Chang, Jiayi Wang, Zezhou Wang, Ningxin Zheng, Zheng Zhong, Cesar A. Stuardo, Dongyang Wang, Mohamed S. Abdelfattah, Haibin Lin, Banghua Zhu, Ang Li, Ziheng Jiang

arXiv
@article{Zeng2026DisagMoE,
	author = {Zeng, Zhichen and Chang, Chi-Chih and Wang, Jiayi and Wang, Zezhou and Zheng, Ningxin and Zhong, Zheng and Stuardo, Cesar A. and Wang, Dongyang and Abdelfattah, Mohamed S. and Lin, Haibin and Zhu, Banghua and Li, Ang and Jiang, Ziheng},
	doi = {10.48550/ARXIV.2605.11005},
	year = {2026},
	publisher = {arXiv},
	title = {DisagMoE: Computation-{Communication} overlapped {MoE} {Training} via {Disaggregated} {AF}-{Pipe} {Parallelism}},
	url = {https://arxiv.org/abs/2605.11005},
}

STEP: Spatially Threaded Execution Pipeline

Darren Lu, Jiayi Wang, Ang Li

The 2026 Workshop on Languages, Tools, and Techniques for Accelerator Design, Mar 2026

PᴺCEL member

Equal contribution