Personal Statement
This person is busy changing the world...
News
Great thanks to Apple for sponsoring the UW ECE chip tape-out courses (Prof. Chris Rudell's analog tape-out series and Ang Li 's digital tape-out series)!
All-Digital Bluetooth Low Energy (BLE) Backscatter ASIC using Standard I/O Pad Drivers in 180 nm CMOS accepted to RFID 2026, congrats to Ryan, Kate, Te Min, Andrew Pan (undergraduate team on Ang Li 's digital VLSI tape-out class, EE 478, Spr 2025) and our collaborators from Prof. Matt Reynolds' research lab!
DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays accepted to ISCA 2026, congrats to Jiayi Wang, Darren Lu, and Zhichen Zeng!
"STEP: Spatially Threaded Execution Pipeline" accepted to the LATTE workshop at ASPLOS 2026, congrats to Darren Lu and Jiayi Wang!
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines accepted as a short paper at FCCM 2026, congrats to Jiayi Wang, Maohua, and Sin-Chen!
Precision-aware Communication in CGRAs accepted as a poster at FCCM 2026. Congrats to Shwet Chitnis, Fergus Xu, Rampranav Navendran, Ayush Kulkarni, and all!
"piPE-SA: Enabling Deeply Pipelined Processing Elements in Systolic Arrays" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jiayi Wang and Chenyi Wang!
"CacheFlex: Explicitly Control What You Need in Your Cache" accepted to the EMC2 workshop at ASPLOS 2026, congrats to Jingqun Zhang, Yung-Jen Cheng, Jiayi Wang, Shwet Chitnis, and all!
Tactic: Adaptive Sparse Attention with Clustering and Distribution Fitting for Long-Context LLMs and Local Linear Attention: An Optimal Interpolation of Linear and Softmax Attention For Test-Time Regression accepted to ICLR 2026, congrats to Zhichen Zeng and our collaborators!
Zhichen Zeng is selected for the 2025-2026 Meta AI Mentorship program. Congrats!
pncel.init();
Welcome our first PhD cohort, Jiayi Wang, Jingqun Zhang, Darren Lu, and Zhichen Zeng!
Selected by UW Clean Energy Institute (CEI)'s collaborative seed grant. Thank you, CEI!
Selected Publications
Full publication listDICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays
Jiayi Wang, Darren Lu, Zhichen Zeng, Ang Li
The 53rd IEEE/ACM International Symposium on Computer Architecture, Jun 2026
@article{Wang2026DICE,
author = {Wang, Jiayi and Da Lu, Ang and Zeng, Zhichen and Li, Ang},
doi = {10.48550/ARXIV.2605.05496},
year = {2026},
publisher = {arXiv},
title = {DICE: Enabling {Efficient} {General}-{Purpose} {SIMT} {Execution} with {Statically} {Scheduled} {Coarse}-{Grained} {Reconfigurable} {Arrays}},
url = {https://arxiv.org/abs/2605.05496},
}
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines
Jiayi Wang, Maohua Nie, Sin-Chen Lin, C. -J. Richard Shi, Ang Li
The 34th IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2026
@article{Wang2026TransDot,
author = {Wang, Jiayi and Nie, Maohua and Lin, Sin-Chen and Shi, C. -J. Richard and Li, Ang},
doi = {10.48550/ARXIV.2605.07245},
year = {2026},
publisher = {arXiv},
title = {TransDot: An {Area}-efficient {Reconfigurable} {Floating}-{Point} {Unit} for {Trans}-{Precision} {Dot}-{Product} {Accumulation} for {FPGA} {AI} {Engines}},
url = {https://arxiv.org/abs/2605.07245},
}
CIFER: A Cache-Coherent 12nm 16mm2 SoC with Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA
Ang Li, Ting-Jung Chang, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff
IEEE Solid-State Circuits Letters, May 2023
@article{Li2023CIFER,
author = {Li, Ang and Chang, Ting-Jung and Gao, Fei and Ta, Tuan and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, Christopher and Wentzlaff, David},
journal = {IEEE Solid-State Circuits Letters},
doi = {10.1109/lssc.2023.3303111},
issn = {2573-9603},
year = {2023},
pages = {229--232},
publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}},
title = {CIFER: A {Cache}-{Coherent} 12-nm 16-mm\textsuperscript{2} {SoC} {With} {Four} 64-{Bit} {RISC}-{V} {Application} {Cores}, 18 32-{Bit} {RISC}-{V} {Compute} {Cores}, and a 1541 {LUT6}/mm\textsuperscript{2} {Synthesizable} {eFPGA}},
url = {http://dx.doi.org/10.1109/LSSC.2023.3303111},
volume = {6},
}
DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET
Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca Carloni, David Wentzlaff
2023 IEEE Custom Integrated Circuits Conference, Apr 2023
@inproceedings{Gao2023DECADES,
author = {Gao, Fei and Chang, Ting-Jung and Li, Ang and Orenes-Vera, Marcelo and Giri, Davide and Jackson, Paul J. and Ning, August and Tziantzioulis, Georgios and Zuckerman, Joseph and Tu, Jinzheng and Xu, Kaifeng and Chirkov, Grigory and Tombesi, Gabriele and Balkind, Jonathan and Martonosi, Margaret and Carloni, Luca and Wentzlaff, David},
booktitle = {2023 {IEEE} {Custom} {Integrated} {Circuits} {Conference} ({CICC})},
doi = {10.1109/cicc57935.2023.10121257},
year = {2023},
month = {4},
pages = {1--2},
organization = {IEEE},
title = {DECADES: A 67mm\textsuperscript{2}, 1.46TOPS, 55 {Giga} {Cache}-{Coherent} 64-bit {RISC}-{V} {Instructions} per second, {Heterogeneous} {Manycore} {SoC} with 109 {Tiles} including {Accelerators}, {Intelligent} {Storage}, and {eFPGA} in 12nm {FinFET}},
url = {http://dx.doi.org/10.1109/CICC57935.2023.10121257},
}
CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2, 1.92 MOPS/LUT, Fully Synthesizable, Cache-Coherent, Embedded FPGA
Ting-Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff
2023 IEEE Custom Integrated Circuits Conference, Mar 2023
@inproceedings{Chang2023CIFER,
author = {Chang, Ting-Jung and Li, Ang and Gao, Fei and Ta, Tuan and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul J. and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, Christopher and Wentzlaff, David},
booktitle = {2023 {IEEE} {Custom} {Integrated} {Circuits} {Conference} ({CICC})},
doi = {10.1109/cicc57935.2023.10121294},
year = {2023},
month = {4},
pages = {1--2},
organization = {IEEE},
title = {CIFER: A 12nm, 16mm\textsuperscript{2}, 22-{Core} {SoC} with a 1541 {LUT6}/mm\textsuperscript{2} 1.92 {MOPS}/{LUT}, {Fully} {Synthesizable}, {CacheCoherent}, {Embedded} {FPGA}},
url = {http://dx.doi.org/10.1109/CICC57935.2023.10121294},
}
Duet: Creating Harmony between Processors and Embedded FPGAs
Ang Li, August Ning, David Wentzlaff
2023 IEEE International Symposium on High-Performance Computer Architecture, Jan 2023
@inproceedings{Li2023Duet,
author = {Li, Ang and Ning, August and Wentzlaff, David},
booktitle = {2023 {IEEE} {International} {Symposium} on {High}-{Performance} {Computer} {Architecture} ({HPCA})},
doi = {10.1109/hpca56546.2023.10070989},
year = {2023},
month = {2},
pages = {745--758},
organization = {IEEE},
title = {Duet: Creating {Harmony} between {Processors} and {Embedded} {FPGAs}},
url = {http://dx.doi.org/10.1109/HPCA56546.2023.10070989},
}
@article{Li2023Duet,
author = {Li, Ang and Ning, August and Wentzlaff, David},
doi = {10.48550/ARXIV.2301.02785},
year = {2023},
publisher = {arXiv},
title = {Duet: Creating {Harmony} between {Processors} and {Embedded} {FPGAs}},
url = {https://arxiv.org/abs/2301.02785},
}
PRGA: An Open-Source FPGA Research and Prototyping Framework
The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb 2021
@inproceedings{Li2021PRGA,
author = {Li, Ang and Wentzlaff, David},
booktitle = {The 2021 {ACM}/{SIGDA} {International} {Symposium} on {Field}-{Programmable} {Gate} {Arrays}},
doi = {10.1145/3431920.3439294},
year = {2021},
month = {feb 17},
pages = {127--137},
organization = {ACM},
title = {PRGA: An {Open}-{Source} {FPGA} {Research} and {Prototyping} {Framework}},
url = {http://dx.doi.org/10.1145/3431920.3439294},
}
Automated Design of FPGAs Facilitated by Cycle-Free Routing
Ang Li, Ting-Jung Chang, David Wentzlaff
2020 30th International Conference on Field-Programmable Logic and Applications, Aug 2020
@inproceedings{Li2020Automated,
author = {Li, Ang and Chang, Ting-Jung and Wentzlaff, David},
booktitle = {2020 30th {International} {Conference} on {Field}-{Programmable} {Logic} and {Applications} ({FPL})},
doi = {10.1109/fpl50879.2020.00042},
year = {2020},
month = {8},
pages = {208--213},
organization = {IEEE},
title = {Automated {Design} of {FPGAs} {Facilitated} by {Cycle}-{Free} {Routing}},
url = {http://dx.doi.org/10.1109/FPL50879.2020.00042},
}
PᴺCEL member
Equal contribution