PᴺCEL | Team

Ang Li

Assistant Professor

ECE 414

angliz (at) uw.edu

Personal Statement

This person is busy changing the world...

Selected Publications

Full publication list

CIFER: A Cache-Coherent 12nm 16mm² SoC with Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm² Synthesizable eFPGA

SSC-L

Prototype Chip

Ang Li, Ting-Jung Chang, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

IEEE Solid-State Circuits Letters, Jun 2023

DOIAuthors' Copy

@article{Li2023CIFER,
	author = {Li, Ang and Chang, Ting-Jung and Gao, Fei and Ta, Tuan and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, Christopher and Wentzlaff, David},
	journal = {IEEE Solid-State Circuits Letters},
	doi = {10.1109/lssc.2023.3303111},
	issn = {2573-9603},
	year = {2023},
	pages = {229--232},
	publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}},
	title = {CIFER: A {Cache}-{Coherent} 12-nm 16-mm\textsuperscript{2} {SoC} {With} {Four} 64-{Bit} {RISC}-{V} {Application} {Cores}, 18 32-{Bit} {RISC}-{V} {Compute} {Cores}, and a 1541 {LUT6}/mm\textsuperscript{2} {Synthesizable} {eFPGA}},
	url = {http://dx.doi.org/10.1109/LSSC.2023.3303111},
	volume = {6},
}

DECADES: A 67mm², 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET

CICC

Best Student Paper Nominee

Prototype Chip

Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca Carloni, David Wentzlaff

2023 IEEE Custom Integrated Circuits Conference, Apr 2023

DOIAuthors' Copy Website

@inproceedings{Gao2023DECADES,
	author = {Gao, Fei and Chang, Ting-Jung and Li, Ang and Orenes-Vera, Marcelo and Giri, Davide and Jackson, Paul J. and Ning, August and Tziantzioulis, Georgios and Zuckerman, Joseph and Tu, Jinzheng and Xu, Kaifeng and Chirkov, Grigory and Tombesi, Gabriele and Balkind, Jonathan and Martonosi, Margaret and Carloni, Luca and Wentzlaff, David},
	booktitle = {2023 {IEEE} {Custom} {Integrated} {Circuits} {Conference} ({CICC})},
	doi = {10.1109/cicc57935.2023.10121257},
	year = {2023},
	month = {4},
	pages = {1--2},
	organization = {IEEE},
	title = {DECADES: A 67mm\textsuperscript{2}, 1.46TOPS, 55 {Giga} {Cache}-{Coherent} 64-bit {RISC}-{V} {Instructions} per second, {Heterogeneous} {Manycore} {SoC} with 109 {Tiles} including {Accelerators}, {Intelligent} {Storage}, and {eFPGA} in 12nm {FinFET}},
	url = {http://dx.doi.org/10.1109/CICC57935.2023.10121257},
}

CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm², 1.92 MOPS/LUT, Fully Synthesizable, Cache-Coherent, Embedded FPGA

CICC

Prototype Chip

Ting-Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

2023 IEEE Custom Integrated Circuits Conference, Apr 2023

DOIAuthors' Copy

@inproceedings{Chang2023CIFER,
	author = {Chang, Ting-Jung and Li, Ang and Gao, Fei and Ta, Tuan and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul J. and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, Christopher and Wentzlaff, David},
	booktitle = {2023 {IEEE} {Custom} {Integrated} {Circuits} {Conference} ({CICC})},
	doi = {10.1109/cicc57935.2023.10121294},
	year = {2023},
	month = {4},
	pages = {1--2},
	organization = {IEEE},
	title = {CIFER: A 12nm, 16mm\textsuperscript{2}, 22-{Core} {SoC} with a 1541 {LUT6}/mm\textsuperscript{2} 1.92 {MOPS}/{LUT}, {Fully} {Synthesizable}, {CacheCoherent}, {Embedded} {FPGA}},
	url = {http://dx.doi.org/10.1109/CICC57935.2023.10121294},
}

Duet: Creating Harmony between Processors and Embedded FPGAs

HPCA

Open-Source

Ang Li, August Ning, David Wentzlaff

2023 IEEE International Symposium on High-Performance Computer Architecture, Feb 2023

DOIAuthors' Copy arXivGitHub

@inproceedings{Li2023Duet,
	author = {Li, Ang and Ning, August and Wentzlaff, David},
	booktitle = {2023 {IEEE} {International} {Symposium} on {High}-{Performance} {Computer} {Architecture} ({HPCA})},
	doi = {10.1109/hpca56546.2023.10070989},
	year = {2023},
	month = {2},
	pages = {745--758},
	organization = {IEEE},
	title = {Duet: Creating {Harmony} between {Processors} and {Embedded} {FPGAs}},
	url = {http://dx.doi.org/10.1109/HPCA56546.2023.10070989},
}

@article{Li2023Duet,
	author = {Li, Ang and Ning, August and Wentzlaff, David},
	doi = {10.48550/ARXIV.2301.02785},
	year = {2023},
	publisher = {arXiv},
	title = {Duet: Creating {Harmony} between {Processors} and {Embedded} {FPGAs}},
	url = {https://arxiv.org/abs/2301.02785},
}

PRGA: An Open-Source FPGA Research and Prototyping Framework

FPGA

Open-Source

Ang Li, David Wentzlaff

The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb 2021

DOIAuthors' Copy Recorded Talk GitHub Website Documentation

@inproceedings{Li2021PRGA,
	author = {Li, Ang and Wentzlaff, David},
	booktitle = {The 2021 {ACM}/{SIGDA} {International} {Symposium} on {Field}-{Programmable} {Gate} {Arrays}},
	doi = {10.1145/3431920.3439294},
	year = {2021},
	month = {feb 17},
	pages = {127--137},
	organization = {ACM},
	title = {PRGA: An {Open}-{Source} {FPGA} {Research} and {Prototyping} {Framework}},
	url = {http://dx.doi.org/10.1145/3431920.3439294},
}

Automated Design of FPGAs Facilitated by Cycle-Free Routing

FPL

Ang Li, Ting-Jung Chang, David Wentzlaff

2020 30th International Conference on Field-Programmable Logic and Applications, Aug 2020

DOIAuthors' Copy

@inproceedings{Li2020Automated,
	author = {Li, Ang and Chang, Ting-Jung and Wentzlaff, David},
	booktitle = {2020 30th {International} {Conference} on {Field}-{Programmable} {Logic} and {Applications} ({FPL})},
	doi = {10.1109/fpl50879.2020.00042},
	year = {2020},
	month = {8},
	pages = {208--213},
	organization = {IEEE},
	title = {Automated {Design} of {FPGAs} {Facilitated} by {Cycle}-{Free} {Routing}},
	url = {http://dx.doi.org/10.1109/FPL50879.2020.00042},
}

PᴺCEL member

Equal contribution