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DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays accepted to ISCA 2026, congrats to Jiayi Wang, Darren Lu, and Zhichen Zeng!
"STEP: Spatially Threaded Execution Pipeline" accepted to the LATTE workshop at ASPLOS 2026, congrats to Darren Lu and Jiayi Wang!
Welcome our first PhD cohort, Jiayi Wang, Jingqun Zhang, Darren Lu, and Zhichen Zeng!
DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays
Jiayi Wang, Darren Lu, Zhichen Zeng, Ang Li
The 53rd IEEE/ACM International Symposium on Computer Architecture, Jun 2026
@article{Wang2026DICE,
author = {Wang, Jiayi and Da Lu, Ang and Zeng, Zhichen and Li, Ang},
doi = {10.48550/ARXIV.2605.05496},
year = {2026},
publisher = {arXiv},
title = {DICE: Enabling {Efficient} {General}-{Purpose} {SIMT} {Execution} with {Statically} {Scheduled} {Coarse}-{Grained} {Reconfigurable} {Arrays}},
url = {https://arxiv.org/abs/2605.05496},
}
STEP: Spatially Threaded Execution Pipeline
The 2026 Workshop on Languages, Tools, and Techniques for Accelerator Design, Mar 2026
PᴺCEL member
Equal contribution