Step-dLLM: Adaptive Step-aware Sparse Attention for Efficient Diffusion LLM Inference accepted to NeurIPS 2026, congrats to Zhichen and our collaborators!
MFSA: A Multi-Format Systolic Array with Native Micro Scaling Support accepted to ICCD 2026, congrats to Jiayi and Kearnan!
CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support accepted to MICRO 2026, congrats to Jingqun, Maohua, Jiayi, Weihang, Rishi, Shwet!
All-Digital Bluetooth Low Energy (BLE) Backscatter ASIC using Standard I/O Pad Drivers in 180 nm CMOS accepted to RFID 2026, congrats to Ryan, Kate, Tyoma, Andrew (undergraduate team on Ang 's digital VLSI tape-out class, EE 478, Spr 2025) and our collaborators from Prof. Matt Reynolds' research lab!
DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays accepted to ISCA 2026, congrats to Jiayi, Darren, and Zhichen!
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines accepted as a short paper at FCCM 2026, congrats to Jiayi, Maohua, and Sin-Chen!