Full Publication List: Ang Li

2025

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Tactic: Adaptive Sparse Attention with Clustering and Distribution Fitting for Long-Context LLMs

Under Review

Kan Zhu, Tian Tang, Qinyu Xu, Yile Gu, Zhichen Zeng, Rohan Kadekodi, Liangyu Zhao, Ang Li, Arvind Krishnamurthy, Baris Kasikci

arXiv
@article{Zhu2025Tactic,	author = {Zhu, Kan and Tang, Tian and Xu, Qinyu and Gu, Yile and Zeng, Zhichen and Kadekodi, Rohan and Zhao, Liangyu and Li, Ang and Krishnamurthy, Arvind and Kasikci, Baris},	doi = {10.48550/ARXIV.2502.12216},	year = {2025},	publisher = {arXiv},	title = {Tactic: Adaptive {Sparse} {Attention} with {Clustering} and {Distribution} {Fitting} for {Long}-{Context} {LLMs}},	url = {https://arxiv.org/abs/2502.12216},}

2023

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Open-Source FPGA on Silicon: Case Studies on PRGA, an Open-Source Framework for Building & Programming Custom FPGAs

OSCAR

Ang Li, Ting-Jung Chang, Fei Gao, David Wentzlaff

2023 Open-Source Computer Architecture Research, Jun 2023

Slides

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Evaluating Shared Memory Heterogeneous Systems Using Traverse-Compute Workloads

OSCAR

Yanwen Xu, Ang Li, Tyler Sorensen

2023 Open-Source Computer Architecture Research, Jun 2023

SlidesRecorded Talk

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CIFER: A Cache-Coherent 12nm 16mm2 SoC with Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

SSC-L
Prototype Chip

Ang Li, Ting-Jung Chang, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

IEEE Solid-State Circuits Letters, Jun 2023

DOIAuthors' Copy
@article{Li2023CIFER,
	author = {Li, Ang and Chang, Ting-Jung and Gao, Fei and Ta, Tuan and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, Christopher and Wentzlaff, David},
	journal = {IEEE Solid-State Circuits Letters},
	doi = {10.1109/lssc.2023.3303111},
	issn = {2573-9603},
	year = {2023},
	pages = {229--232},
	publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}},
	title = {CIFER: A {Cache}-{Coherent} 12-nm 16-mm\textsuperscript{2} {SoC} {With} {Four} 64-{Bit} {RISC}-{V} {Application} {Cores}, 18 32-{Bit} {RISC}-{V} {Compute} {Cores}, and a 1541 {LUT6}/mm\textsuperscript{2} {Synthesizable} {eFPGA}},
	url = {http://dx.doi.org/10.1109/LSSC.2023.3303111},
	volume = {6},
}

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DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET

CICC
Best Student Paper Nominee
Prototype Chip

Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca Carloni, David Wentzlaff

2023 IEEE Custom Integrated Circuits Conference, Apr 2023

DOIAuthors' CopyWebsite
@inproceedings{Gao2023DECADES,
	author = {Gao, Fei and Chang, Ting-Jung and Li, Ang and Orenes-Vera, Marcelo and Giri, Davide and Jackson, Paul J. and Ning, August and Tziantzioulis, Georgios and Zuckerman, Joseph and Tu, Jinzheng and Xu, Kaifeng and Chirkov, Grigory and Tombesi, Gabriele and Balkind, Jonathan and Martonosi, Margaret and Carloni, Luca and Wentzlaff, David},
	booktitle = {2023 {IEEE} {Custom} {Integrated} {Circuits} {Conference} ({CICC})},
	doi = {10.1109/cicc57935.2023.10121257},
	year = {2023},
	month = {4},
	pages = {1--2},
	organization = {IEEE},
	title = {DECADES: A 67mm\textsuperscript{2}, 1.46TOPS, 55 {Giga} {Cache}-{Coherent} 64-bit {RISC}-{V} {Instructions} per second, {Heterogeneous} {Manycore} {SoC} with 109 {Tiles} including {Accelerators}, {Intelligent} {Storage}, and {eFPGA} in 12nm {FinFET}},
	url = {http://dx.doi.org/10.1109/CICC57935.2023.10121257},
}

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Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads

ISPASS
Open-Source

Yanwen Xu, Ang Li, Tyler Sorensen

2023 IEEE International Symposium on Performance Analysis of Systems and Software, Apr 2023

DOIAuthors' Copy
@inproceedings{Xu2023Redwood,
	author = {Xu, Yanwen and Li, Ang and Sorensen, Tyler},
	booktitle = {2023 {IEEE} {International} {Symposium} on {Performance} {Analysis} of {Systems} and {Software} ({ISPASS})},
	doi = {10.1109/ispass57527.2023.00028},
	year = {2023},
	month = {4},
	pages = {201--213},
	organization = {IEEE},
	title = {Redwood: Flexible and {Portable} {Heterogeneous} {Tree} {Traversal} {Workloads}},
	url = {http://dx.doi.org/10.1109/ISPASS57527.2023.00028},
}

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CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2, 1.92 MOPS/LUT, Fully Synthesizable, Cache-Coherent, Embedded FPGA

CICC
Prototype Chip

Ting-Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

2023 IEEE Custom Integrated Circuits Conference, Apr 2023

DOIAuthors' Copy
@inproceedings{Chang2023CIFER,
	author = {Chang, Ting-Jung and Li, Ang and Gao, Fei and Ta, Tuan and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul J. and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, Christopher and Wentzlaff, David},
	booktitle = {2023 {IEEE} {Custom} {Integrated} {Circuits} {Conference} ({CICC})},
	doi = {10.1109/cicc57935.2023.10121294},
	year = {2023},
	month = {4},
	pages = {1--2},
	organization = {IEEE},
	title = {CIFER: A 12nm, 16mm\textsuperscript{2}, 22-{Core} {SoC} with a 1541 {LUT6}/mm\textsuperscript{2} 1.92 {MOPS}/{LUT}, {Fully} {Synthesizable}, {CacheCoherent}, {Embedded} {FPGA}},
	url = {http://dx.doi.org/10.1109/CICC57935.2023.10121294},
}

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Duet: Creating Harmony between Processors and Embedded FPGAs

HPCA
Open-Source

Ang Li, August Ning, David Wentzlaff

2023 IEEE International Symposium on High-Performance Computer Architecture, Feb 2023

DOIAuthors' CopyarXivGitHub
@inproceedings{Li2023Duet,
	author = {Li, Ang and Ning, August and Wentzlaff, David},
	booktitle = {2023 {IEEE} {International} {Symposium} on {High}-{Performance} {Computer} {Architecture} ({HPCA})},
	doi = {10.1109/hpca56546.2023.10070989},
	year = {2023},
	month = {2},
	pages = {745--758},
	organization = {IEEE},
	title = {Duet: Creating {Harmony} between {Processors} and {Embedded} {FPGAs}},
	url = {http://dx.doi.org/10.1109/HPCA56546.2023.10070989},
}


@article{Li2023Duet,
	author = {Li, Ang and Ning, August and Wentzlaff, David},
	doi = {10.48550/ARXIV.2301.02785},
	year = {2023},
	publisher = {arXiv},
	title = {Duet: Creating {Harmony} between {Processors} and {Embedded} {FPGAs}},
	url = {https://arxiv.org/abs/2301.02785},
}

2021

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PRGA: An Open-Source FPGA Research and Prototyping Framework

FPGA
Open-Source

Ang Li, David Wentzlaff

The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb 2021

DOIAuthors' CopyRecorded TalkGitHubWebsiteDocumentation
@inproceedings{Li2021PRGA,
	author = {Li, Ang and Wentzlaff, David},
	booktitle = {The 2021 {ACM}/{SIGDA} {International} {Symposium} on {Field}-{Programmable} {Gate} {Arrays}},
	doi = {10.1145/3431920.3439294},
	year = {2021},
	month = {feb 17},
	pages = {127--137},
	organization = {ACM},
	title = {PRGA: An {Open}-{Source} {FPGA} {Research} and {Prototyping} {Framework}},
	url = {http://dx.doi.org/10.1145/3431920.3439294},
}

2020

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Automated Design of FPGAs Facilitated by Cycle-Free Routing

FPL

Ang Li, Ting-Jung Chang, David Wentzlaff

2020 30th International Conference on Field-Programmable Logic and Applications, Aug 2020

DOIAuthors' Copy
@inproceedings{Li2020Automated,
	author = {Li, Ang and Chang, Ting-Jung and Wentzlaff, David},
	booktitle = {2020 30th {International} {Conference} on {Field}-{Programmable} {Logic} and {Applications} ({FPL})},
	doi = {10.1109/fpl50879.2020.00042},
	year = {2020},
	month = {8},
	pages = {208--213},
	organization = {IEEE},
	title = {Automated {Design} of {FPGAs} {Facilitated} by {Cycle}-{Free} {Routing}},
	url = {http://dx.doi.org/10.1109/FPL50879.2020.00042},
}

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OpenPiton at 5: A Nexus for Open and Agile Hardware Design

IEEE Micro

Jonathan Balkind, Ting-Jung Chang, Paul Jackson, Georgios Tziantzioulis, Ang Li, Fei Gao, Alexey Lavrov, Grigory Chirkov, Jinzheng Tu, Mohammad Shahrad, David Wentzlaff

IEEE Micro, Jul 2020

DOIAuthors' Copy
@article{Balkind2020OpenPiton,
	author = {Balkind, Jonathan and Chang, Ting-Jung and Jackson, Paul J. and Tziantzioulis, Georgios and Li, Ang and Gao, Fei and Lavrov, Alexey and Chirkov, Grigory and Tu, Jinzheng and Shahrad, Mohammad and Wentzlaff, David},
	journal = {IEEE Micro},
	doi = {10.1109/mm.2020.2997706},
	issn = {0272-1732},
	number = {4},
	year = {2020},
	month = {jul 1},
	pages = {22--31},
	publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}},
	title = {OpenPiton at 5: A {Nexus} for {Open} and {Agile} {Hardware} {Design}},
	url = {http://dx.doi.org/10.1109/MM.2020.2997706},
	volume = {40},
}

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BYOC: A “Bring Your Own Core” Framework for Heterogeneous-ISA Research

ASPLOS
Open-Source

Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini, David Wentzlaff

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Mar 2020

DOIAuthors' Copy
@inproceedings{Balkind2020BYOC,
	author = {Balkind, Jonathan and Lim, Katie and Schaffner, Michael and Gao, Fei and Chirkov, Grigory and Li, Ang and Lavrov, Alexey and Nguyen, Tri M. and Fu, Yaosheng and Zaruba, Florian and Gulati, Kunal and Benini, Luca and Wentzlaff, David},
	booktitle = {Proceedings of the {Twenty}-{Fifth} {International} {Conference} on {Architectural} {Support} for {Programming} {Languages} and {Operating} {Systems}},
	doi = {10.1145/3373376.3378479},
	year = {2020},
	month = {mar 9},
	pages = {699--714},
	organization = {ACM},
	title = {BYOC},
	url = {http://dx.doi.org/10.1145/3373376.3378479},
}

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Cycle-Free FPGA Routing Graphs

FPGA

Ang Li, David Wentzlaff

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb 2020

DOIAuthors' CopyPoster
@inproceedings{Li2020Cycle,
	author = {Li, Ang and Wentzlaff, David},
	booktitle = {Proceedings of the 2020 {ACM}/{SIGDA} {International} {Symposium} on {Field}-{Programmable} {Gate} {Arrays}},
	doi = {10.1145/3373087.3375354},
	year = {2020},
	month = {feb 23},
	pages = {322--322},
	organization = {ACM},
	title = {Cycle-{Free} {FPGA} {Routing} {Graphs}},
	url = {http://dx.doi.org/10.1145/3373087.3375354},
}

2019

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PRGA: An Open-source Framework for Building and Using Custom FPGAs

OSDA

Ang Li, David Wentzlaff

The 1st Workshop on Open Source Design Automation, Mar 2019

Poster

2018

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OpenPiton: An Emerging Standard for Open-Source EDA Tool Development

WOSET

Jonathan Balkind, Alexey Lavrov, Michael McKeown, Yaosheng Fu, Tri Nguyen, Mohammad Shahrad, Ang Li, Katie Lim, Yanqi Zhou, Ting-Jung Chang, Paul Jackson, Adi Fuchs, Samuel Payne, Xiaohua Liang, Matthew Matl, David Wentzlaff

The 1st Workshop on Open-Source EDA Technology, Nov 2018

Authors' Copy

2015

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Leveraging Emerging Nonvolatile Memory in High-Level Synthesis with Loop Transformations

ISLPED

Shuangchen Li, Ang Li, Yuan Zhe, Yongpan Liu, Peng Li, Guangyu Sun, Yu Wang, Huazhong Yang, Yuan Xie

2015 IEEE/ACM International Symposium on Low Power Electronics and Design, Jul 2015

DOI
@inproceedings{Li2015Leveraging,
	author = {Li, Shuangchen and Li, Ang and Zhe, Yuan and Liu, Yongpan and Li, Peng and Sun, Guangyu and Wang, Yu and Yang, Huazhong and {Yuan Xie}},
	booktitle = {2015 {IEEE}/{ACM} {International} {Symposium} on {Low} {Power} {Electronics} and {Design} ({ISLPED})},
	doi = {10.1109/islped.2015.7273491},
	year = {2015},
	month = {7},
	pages = {61--66},
	organization = {IEEE},
	title = {Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations},
	url = {http://dx.doi.org/10.1109/ISLPED.2015.7273491},
}

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Nonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis

ASP-DAC

Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie, Huazhong Yang

The 20th Asia and South Pacific Design Automation Conference, Jan 2015

DOI
@inproceedings{Li2015Nonvolatile,
	author = {Li, Shuangchen and {Ang Li} and Liu, Yongpan and Xie, Yuan and {Huazhong Yang}},
	booktitle = {The 20th {Asia} and {South} {Pacific} {Design} {Automation} {Conference}},
	doi = {10.1109/aspdac.2015.7058999},
	year = {2015},
	month = {1},
	pages = {166--171},
	organization = {IEEE},
	title = {Nonvolatile memory allocation and hierarchy optimization for high-level synthesis},
	url = {http://dx.doi.org/10.1109/ASPDAC.2015.7058999},
}

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